It is a requirement of data transmission systems that the circuitry of a location that receives data be synchronized with the clock of the source from which the data is transmitted. This is necessary so that the receiving location can regenerate data that corresponds to that which was transmitted.
An obvious way to synchronize a data receiver with a data transmitter is to apply a synchronizing signal over a separate path extending between the transmitter and the receiver. This expedient is satisfactory when the two locations are proximate each other, such as in the same equipment room. However, it is not normally economically feasible to provide a separate synchronizing path when the two locations are remote from one another.
It is known to provide circuits that recover the clock of a data source from the signal transmitted by the source to a receiving location. This expedient obviates the need for a separate synchronizing path. However, it does so at the cost of added clock recovery circuitry.
Thus, it is known to recover the clock from teletypewriter signals transmitted over a line in a serial RS232 format at a relatively low rate of 30 characters per second. These clock recovery circuits detect many samples (often 16) of each received bit and store the samples in a shift register. The shift register is read out in parallel and the output applied to an evaluation circuit which uses the principle of majority rule to determine whether the 16 samples represent a binary "0" or a binary "1". Circuitry of this type is commonly used in UARTs (universal asynchronous receivers/transmitters). UART circuits are not fast, but speed is not important since the data rate is often only 30 characters per second. Also, signals received over teletypewriter lines are often noisy. However, the sampling rate of 16 times the incoming clock rate tends to minimize bit errors due to noise.
An improved clock recovery circuit is disclosed in an article entitled "For data-com links, Manchester chip could be best" by Lester Sanders shown on pages 201 through 209 of Electronic Design of Aug. 5, 1982. This circuit is embodied in LSI and uses 12 samples of each received bit in the incoming data stream to derive clock signals. The 12 samples are stored in a shift register which is read out in parallel to derive the incoming clock in much the same manner as in UART devices.
The above-described circuits operate satisfactory to derive the clock of incoming data. However, the sampling rate of 12 or 16 times the incoming clock limits the incoming clock frequency at which these circuits can operate. These circuits also have the disadvantage that a steady incoming stream of "0's" produces no clock at all since these circuits are waveform transition driven.